Vitruvius: An Area Efficient RISC V Decoupled Vector Francesco Minervini Oscar Palomar Perez
Vitruvius: An AreaEfficient RISCV Decoupled Vector Accelerator for High Performance Computing Francesco Minervini Oscar Palomar Perez, Barcelona Supercomputing Center BSC The availability of domainspecific instruction set extensions, like vector processing, make RISCV a good candidate for supporting the integration of specialized hardware in processor cores. This talk presents Vitruvius, the first RISCV vector accelerator developed at BSC for the Supercomputing domain. Vitruvius is compliant with the RISCV vector extension specification and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard in a plugandplay fashion. Vitruvius natively supports long vectors: 256 Double Precision (DP) floatingpoint elements in a single vector instruction. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File (VRF) and functional units (one integer, one floatingpoint). It adopts a novel hybrid inorder, outo
|
|