Tensor Flow to RTL with High Level Synthesis Cadence Design Systems
April 17, 2020 Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. Highlevel synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of highperformance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS. More information about Stratus HighLevel Synthesis:
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