RISC V Technical Session, Hardware Based Detection of Stack Buffer Overflow Attacks on RISC V

This Tech Session evaluates the effectiveness of hardwarebased approaches in detecting stack buffer overflow (SBO) attacks on RISCV systems. Presenters conducted simulations on the PULP platform, examining microarchitecture events using semisupervised anomaly detection techniques. The findings highlighted challenges in detection performance, suggesting that a combined approach using both software and hardware detectors might be more effective, with hardware serving as the primary defense. These hardwarebased approaches offer significant benefits that could enhance RISCVbased architectures. This work was supported by Project SERICS through the MUR National Recovery and Resilience Plan, funded by the European UnionNextGenerationEU under Grant PE00000014, and by the VitaminV Project, funded by the European Union under Project 101093062. Presenters: Alessandro Savino, Associate Professor Politecnico di Torino Cristiano Chenet, Candidate Politecnico di Torino Stefano Di Carlo, Full Professor Politecnico di Torino