Reinforcement Learning for Hardware Design feat. Anna Goldie, Stanford MLSys Seminar Episode 14

Episode 14 of the Stanford MLSys Seminar Series Chip Floorplanning with Deep Reinforcement Learning Speaker: Piero Molino Abstract: In this talk, I will describe a reinforcement learning (RL) method for chip floorplanning, the engineering problem of designing the physical layout of a computer chip. Chip floorplanning ordinarily requires weeks or months of effort by physical design engineers to produce manufacturable layouts. Our method generates floorplans in under six hours that are superior or comparable to humans in all key metrics, including power consumption, performance, and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop a novel edgebased graph convolutional neural network architecture capable of learning rich and transferrable representations of the chip. Our method was used in the design of the next generation of Googles artificial intelligence (AI) accelerators (TPU). Speaker bio: Anna Goldie is a Staff Researcher at Google Brain and cof