AI RISC Custom Extensions to RISC V for Energy efficient AI Inference at the Vaibhav Verma

AIRISC Custom Extensions to RISCV for Energyefficient AI Inference at the Edge of IoT Vaibhav Verma, University of Virginia Numerous hardware accelerators have been proposed to meet the performance and energyefficiency requirements of AI applications. But these accelerators have been developed in separate silos with little to no infrastructure for integrating these accelerators in the toplevel system stack. We present AIRISC as a solution to bridge this research gap. AIRISC is a hardware, software codesign methodology where AI accelerators are integrated in the RISCV processor pipeline at a finegranularity and treated as regular functional units during the execution of instructions. AIRISC also extends the RISCV ISA with custom instructions which directly target these AI functional units (AFU) resulting in a tight integration of AI accelerators with the processor. AIRISC adopts a 2step compilation strategy where opensource TVM is used as the frontend compiler while LLVM based custom Ccompi